Multiple-resolution SIMD decoding architecture for QC-LDPC codes

Abstract

The 5G New-Radio (NR) standard requires high throughput of $20Gbps$. To achieve this throughput, a QC-LDPC decoder, which is located in the physical layer of the network and corrects the error that have occurred in the data, is very important. In the digital processing of the channel coding method, it is necessary to quantize the log-likelihood ratio (LLR) values to certain number of bits. Previous QC-LDPC decoders are processing data with a single quantization, and this would meet the $20Gbps$ requirement, but the power consumption is too high and thus have a low energy-efficiency. Therefore, we look again the practical meaning of $20 Gbps$ in the standard, and quantize differently with respect to the signal-to-noise ratio (SNR). To process every number of quantization bit, we adopt SIMD concept and propose an energy-efficient multiple-resolution decoder which can meet the peak data rate as well. The proposed decoder was designed in $28nm$ CMOS technology, and consumes less power than the conventional partially parallel architecture, and achieve the high energy-efficiency.