(A) study of Gate-All-Around nanowire transistor with IGZO channel by TCAD simulations

Abstract

This paper investigates the device characteristics in the Gate-All-Around nanowire transistor through TCAD simulation modeling of the proposed IGZO channel material for 3D DRAM. Currently, as DRAM cell scaling reaches its limits, attempts are being made to transition to stacked structures and vertical gates. Research is underway to leverage the low leakage current and high-temperature stability of IGZO material. Considering this, suitable structures and target characteristics are proposed, and key scale factors such as channel length and radius are varied to examine the transfer characteristics with respect to gate voltage. To enhance simulation accuracy, the IGZO channel device is modeled based on experimental results, demonstrating a high degree of consistency between the simulation outcomes and literature values.