Fully dynamic discrete-time delta-sigma modulator with digital noise coupling

Abstract

Recently, the demand for a high-resolution low-power analog-to-digital converter (ADC) for sensor and audio band applications has been increasing. In response to these requirements, many studies are being conducted on delta-sigma modulator (DSM) that are suitable for high-resolution applications in low-frequency bands. While discrete-time (DT) DSM is robust to process-voltage-temperature (PVT) variation and can operate across multiple frequency bands, DT DSM consumes larger power in amplifiers compared to CT DSM. In this research, the power consumption of DT DSM is significantly reduced by utilizing a dynamic amplifier (DA). In addition, the successive approximation register (SAR) assisted digital noise coupling (DNC) technique is employed to obtain additional noise-shaping orders without an amplifier. Therefore, this research achieves high resolution with low power consumption using a DA and SAR-assisted DNC. This work is implemented in a 28nm CMOS technology and its core layout occupies 0.123mm2. In 25kHz bandwidth with an oversampling ratio (OSR) of 128, this work could achieve signal-to-distortion and noise ratio (SNDR) of 103.5dB with 76.84μW power consumption in post-layout simulation. The Schreier figure of merit (FoMS) derived from the post-layout simulation results is 188.6dB, achieving state-of-the-art performance compared to other ADCs with similar bandwidths.