(A) high-resolution dual-residue pipelined ADC with fully-passive interpolating noise-shaping SAR

Abstract

In this thesis, fully-dynamic noise-shaping interpolating successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to be utilized at the pipeline backend for an energy-efficient high-resolution dual-residue pipeline-SAR architecture. Segmentation technique for the capacitive interpolating digital-to-analog converter (DAC) is also proposed to solve the parasitic sensitiveness of the previous capacitive interpolation, and thereby, to enhance the resolution of the proposed architecture: Signal-to-quantization noise ratio (SQNR) of +20-dB is increased by the proposed segmentation technique. The gain-error free pipeline architecture and the high-resolution capability of the proposed backend noise-shaping interpolating-SAR ADC allow small residue gain, which does not degrade the advantages of the dual-residue architecture, even in the high-resolution pipeline ADC design. Therefore, the strict requirements conventionally imposed on the residue amplifier are significantly alleviated at the aspect of power, calibration, and linearity. Moreover, by utilizing the first stage of the residue amplifier not only for the dual-residue amplification but also for the kT/C-noise cancellation in the first-stage ADC, gain and offset requirements could be further relaxed, while the original merits are preserved. The prototype pipeline ADC was fabricated in a 180-nm CMOS technology and achieves a signal-to-noise and distortion ratio (SNDR) of 81.2-dB in a 1.5-MHz bandwidth at an over-sampling ratio (OSR) of 8 with an SNDR Schreier figure of merit (FoM) of 170.4-dB without any calibration.