Optimizing ADC utilization through value-aware bypass in ReRAM-based DNN accelerator

Abstract

ReRAM-based Processing-In-Memory (PIM) has been widely studied as a promising approach for Deep Neural Networks (DNN) accelerator with its energy-efficient analog MAC operations. However, the domain conversion process for the analog operation requires frequent accesses to power-hungry Analog-to-Digital Converter (ADC), hindering the overall energy efficiency. Although previous research has been suggested to address this problem, the ADC cost has not been sufficiently reduced because of its unsuitable approach for ReRAM. In this thesis, mixed-signal circuit-based value-aware bypass techniques to optimize the ADC utilization of the ReRAM-based PIM are proposed. By utilizing the property of bit-line (BL) level value distribution, the proposed techniques bypass the redundant ADC operations depending on the magnitude of value. Evaluation results show that bypass techniques successfully reduce ADC access and improve overall energy efficiency by 2.48$\times$-3.07$\times$ compared to ISAAC.