Algorithm-architecture co-design for accelerating deep reinforcement learning on robotics applications로보틱스 활용에서의 심층 강화 학습 가속을 위한 하드웨어 및 알고리즘 최적화

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Deep Reinforcement Learning (DRL) plays a critical role in controlling and manipulating futureintelligent machines like robots and drones. However, DRL repeats inference and training that are computationallyexpensive on resource-constraint mobile/embedded platforms. Even worse, DRL producesa severe hardware underutilization problem due to its unique execution pattern.This paper presents CoRe, an algorithm-architecture co-designed system that simultaneously achievesspeedup and energy efficiency of the DRL algorithm while maintaining its accuracy. To overcome theinefficiency of DRL, we propose Train Early Start, a new execution pattern for building the efficienton-policy DRL algorithm. Train Early Start parallelizes the inference and training execution, hidingthe serialized performance bottleneck. To maximize the benefit of Train Early Start, we design CoRearchitecture, a multi-core NPU system that exploits the task-level parallelism of Train Early Start. As a result, CoRe achieves on average 2.81× speedup and 6.27× energy efficiency over the state-of-the-artmobile SoC.
Advisors
김이섭researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2022
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2022.8,[iii, 44 p. :]

Keywords

심층 강화 학습▼a하드웨어 가속기▼a인공지능 가속기 디자인; Deep reinforcement learning▼aHardware accelerator▼aAI accelerator design

URI
http://hdl.handle.net/10203/320425
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1044825&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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