A V-band frequency tripler is presented, consisting of both passive and active frequency triplers. The passive tripler is composed of back-to-back connected accumulation-mode MOS (AMOS) varactors and generates third-order harmonics (3 f(0)) from a fundamental ( f(0)) input. The input of the active tripler is shunted to the passive one and also generates 3 f(0) from f(0) input. Simultaneously, 3 f(0) generated from the passive tripler is amplified by the active core and added to the output. This enables the tripler to have high dc-to-RF efficiency. It is implemented in a 28-nm bulk CMOS process, achieving output power of -1.3 dBm and 5.2% conversion efficiency (CE) while consuming 9.4 mW of power from a 1.1-V supply.