Mitigating IR-Drop with Design Technology Co-Optimization for Sub-Nanometer Node Technology

Abstract

In this paper, we have proposed various approaches for reducing IR (Voltage)-drop with the best trade-off between the PPA (performance, power, area) and the IR tolerance for sub-nanometer node designs and technologies. The proposed approaches include the optimization of power distribute network (PDN), clock-cell placement, and cell placement in logic paths.