Mitigating IR-Drop with Design Technology Co-Optimization for Sub-Nanometer Node Technology
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, Dohyeon | ko |
| dc.contributor.author | Hwang, Heecheol | ko |
| dc.contributor.author | Oh, Hyunteck | ko |
| dc.contributor.author | Ban, Yongchan James | ko |
| dc.date.accessioned | 2023-09-07T08:00:33Z | - |
| dc.date.available | 2023-09-07T08:00:33Z | - |
| dc.date.created | 2023-09-07 | - |
| dc.date.issued | 2021-10-06 | - |
| dc.identifier.citation | 2021 18th International SoC Design Conference (ISOCC), pp.163 - 164 | - |
| dc.identifier.issn | 2163-9612 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/312317 | - |
| dc.description.abstract | In this paper, we have proposed various approaches for reducing IR (Voltage)-drop with the best trade-off between the PPA (performance, power, area) and the IR tolerance for sub-nanometer node designs and technologies. The proposed approaches include the optimization of power distribute network (PDN), clock-cell placement, and cell placement in logic paths. | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | Mitigating IR-Drop with Design Technology Co-Optimization for Sub-Nanometer Node Technology | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000861550500073 | - |
| dc.identifier.scopusid | 2-s2.0-85123342023 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 163 | - |
| dc.citation.endingpage | 164 | - |
| dc.citation.publicationname | 2021 18th International SoC Design Conference (ISOCC) | - |
| dc.identifier.conferencecountry | KO | - |
| dc.identifier.conferencelocation | Jeju Island | - |
| dc.identifier.doi | 10.1109/isocc53507.2021.9614021 | - |
| dc.contributor.localauthor | Lee, Dohyeon | - |
| dc.contributor.nonIdAuthor | Hwang, Heecheol | - |
| dc.contributor.nonIdAuthor | Oh, Hyunteck | - |
| dc.contributor.nonIdAuthor | Ban, Yongchan James | - |
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