Low-power high data-rate PLLs for IoT applications

Abstract

Two designs of phase lock loops (PLL) for IoT applications are presented in this thesis. The PLL, which is one of the most energy demanding block in a transceiver, plays an extremely significant role in improving the performance of the tranceiver. The first PLL, which is based on type-II structure, exhibits 18.9ps of rms jitter while dissipating lower than 600uW of power. The second PLL, which employs a master-slave sampling phase detector, has simulated spur level of -58dBc at 900MHz and a figure-of-merit (FoM) of -243dB. A phase noise reduced, supply noise insensitive ring voltage-controlled oscillator (VCO) is also proposed.