(A) study on the performance improvement of devices by band engineering with inserting dipole formation layer

Abstract

Tunnel field-effect transistors (TFETs) have been proposed to outperform complementary metal-oxide-semiconductor (CMOS) transistors in low-power applications owing to their low leakage current and sub-threshold swing below 60 mV/dec. However, Si TFETs exhibit extremely low on-current compared to MOSFETs due to the wide indirect band gap. To achieve high on-current, we have proposed the Si TFET with the ultra-thin dipole formation layer (DFL) of III-V materials inserted at the source-channel junction. We have found that the insertion of DFL forms charge transfer dipoles at the interfaces, by means of the first-principle calculations. The band alignment of staggered gap is formed at the TFET source-to-channel junction due to the electrostatic potential shifted by the insertion of the DFL, resulting in the reduction of effective tunnel barrier. As a consequence, we demonstrated its potential as low power device by achieving higher on-current and smaller SS than all-Si TFETs.