Area-efficient QC-LDPC decoding architecture with thermometer code-based sorting and relative quasi-cyclic shifting

Abstract

As the 5G New-Radio (NR) standard requires high throughput and low latency, the low-density parity-check (LDPC) codes, which have inherent parallelism and lower decoding complexity than the Turbo codes, were adopted as the channel coding of the data channel. The check node unit of the previous LDPC min-sum decoders used a sorting method employing the min-tree structure in the absolute binary number system to perform a nonlinear operation to find the two minima and index of the first minimum value. However, the min-tree structure causes high hardware complexity and long latency. Therefore, we propose a structure that can efficiently find the two minima and index of the first one by converting to the thermometer code-based number system. In addition, we propose single QSN stage architecture that can reduce the use of huge cyclic shifting logic applied to support various lifting sizes by utilizing relative shift coefficients in layered scheduling. The proposed decoder is implemented in a 65nm CMOS technology, and by applying a partially parallel structure, it satisfies the various operation modes and throughput requirements of the 5G NR, and achieves the highest throughput per area compared to the state-of-the-art LDPC decoders.