Column architecture design of parallel data control and interface for processing in memory(PIM)

Abstract

Artificial intelligence has been steadily advancing. Naturally, as more data becomes available, machine learning technology is becoming increasingly important. However, there is a disadvantage that a lot of time and energy is consumed in the process of computing and processing a lot of concentrated data at once. Although the system tries to overcome limitations such as linking with memory with high bandwidth or minimizing arrival delay, the existing structure has limitations to dramatically improve its shortcomings. To overcome these problems, the concept of processor-in-memory (PIM) has emerged and is actively being researched. This paper proposes a column architecture optimization method for constructing GDDR6-based PIM that guarantees tCCD, which is an operating characteristic at high speed. Compared to the existing GDDR6, the flow of the added commands was defined and designed, logic and operation characteristics were verified and margin were guaranteed through simulation, and the final operation boundary was confirmed through actual measurement. If the column structure design proposed in this study is taken as a foundation, it can be expected to contribute to a more advanced form of PIM design and eventually commercialization.