(A) mitigation of resistance variations in ReRAM-based DNN accelerators by optimizing ADC reference voltages

Abstract

The ReRAM-based deep neural network (DNN) accelerator has been in the spotlight as a processing-in-memory (PIM) platform as it efficiently enables vector-matrix multiplication operations in the analog domain. Unfortunately, the resistance variation of the ReRAM cell significantly hinders the inference accuracy in these accelerators. Recent works have attempted to improve the accuracy of the dot product by reducing the number of concurrently activated wordlines. However, this sacrifices parallelism, the main advantage of ReRAM-based dot product machines. This thesis proposes a new technique that improves the accuracy of ReRAM-based dot product operations without reducing the number of concurrently activated wordlines. By optimizing the reference voltage of the ADC, the proposed scheme can obtain accurate digital output from the inaccurate bit-line current. Evaluation results show that the proposed work effectively improves DNN accuracy without sacrificing parallelism.