Low-latency encoding strategy for highly reliable NAND flash memory

Abstract

NAND flash memory uses multi-level cell (MLC), triple-level cell (TLC), and quadruple-level cell (QLC) which store several bits in a single cell, and increases the density and capacity of NAND flash memory. However, storing more bits in a single cell degrade the lifetime and reliability of NAND flash memory, and shrinking the fabrication process accelerates the worn-out speed of flash memory cells. To address this problem, N-level cell leveling has been proposed, which uses N states with low error rates to store data. However, conventional NLC schemes require the exact state information of flash memory cells, making an inefficient read-sensing process to get the information. This paper analyzes the performance overhead of conventional NLC schemes in the read operation. Moreover, we proposed a low-latency encoding scheme (LLE) that optimizes read operation by minimizing the number of read-sensing in NLC flash memory. The proposed scheme reduces read latency in flash memory and improves reliability characteristics. With realistic error models and real-world workloads, Experimental results show a reduced read latency and raw bit error rate by 34.1%, and 87.0%, respectively, on average.