Development of 3-terminal synaptic transistor based on charge injection for linear conductance update

Abstract

In the advent of the Big Data era and the arising of the artificial intelligence technology, the availability to handle the huge data is highly required. However, the conventional von Neumann architecture, which consists of physically separated memory and processing unit, triggers bottleneck to deal with data-intensive task due to obligated data transfer. Neuromorphic computing is one of the promising alternative, which considered to overcome the bottleneck with synapse device, where the data can be computed and processed in the same place. Among them, The 3-terminal synapse device is attractive due to its high stability and weight controllability. However, previous researches have reported several drawbacks such as high nonlinearity, CMOS incompatibility, and low dynamic range. In this work, the field-effect based 3-terminal device is introduced, utilizing the thermionic emission based charge injection from and to gate. The device achieves high linearity, uniformity, low power consumption, and reasonable endurance and retention with CMOS compatible material and process, which implies the device is qualified for large-scale crossbar array based neuromorphic computing.