Learning Super-scale Microbump Pin Assignment Optimization for Real-world PCB Design with Graph Representation

Abstract

he requirement for higher bandwidth in computing systems has increased. Hence, the number of I/Os of 2.5D/3D ICs is also increasing for dense interconnections. Accordingly, the pin count of the microbump package is getting larger along with its signal integrity issues. In this paper, we propose a deep reinforcement learning (DRL)-based pin assignment optimization method that represents microbumps on graphs to minimize signal integrity degradation. The pin assignment task of microbumps is formulated by modifying the maximum independent set (MIS) problem which is a graph combinatorial optimization task. The proposed method is designed by making adjustments to a state-of-the-art DRL-based MIS solver. The graph-based learning method brings advantages in that it can assign pins to pin maps of any shape on a very large scale. We verify that the proposed DRL-based method is effective by comparing it with a meta-heuristic method, a conventional method for solving optimization tasks, called genetic algorithm.