This paper presents a D-band frequency variablegain low-noise amplifier (VG-LNA), which is fabricated using a 40 nm RF CMOS process. This designed LNA comprises a 4stage differential amplifiers, and impedance matching is achieved using a transformer. The first stage was designed with a common gate(CG) structure for low noise at high frequency, and sufficient gain was achieved through triple-inductive coupling method. The fourth stage used a cascode structure and common gate cross summing method for high gain and stable gain control function. It shows a gain of 21.2 dB and a noise Figure of 8.1 dB at 148 GHz. The measured minimum I P{1 d B} is-28.5 dBm and gain control range is 12.5 dB at 148 GHz. The total area of the chip, including the pads, is 0.24\mathrm{~mm}2, and the chip consumes 41 mW of DC power.