A high-speed pattern decoder in MPEG-4 padding block hardware accelerator

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 824
  • Download : 1132
DC FieldValueLanguage
dc.contributor.authorMo, H.-C.-
dc.contributor.authorKim, J.-S.-
dc.contributor.authorKim, Lee-Sup-
dc.date.accessioned2007-05-23T05:01:48Z-
dc.date.available2007-05-23T05:01:48Z-
dc.date.created2012-02-06-
dc.date.issued2001-05-06-
dc.identifier.citationIEEE International Symposium on Circuits and Systems (ISCAS 2001), v.2, no., pp. --
dc.identifier.issn0271-4310-
dc.identifier.urihttp://hdl.handle.net/10203/297-
dc.descriptionISCAS.2001 Mayen
dc.description.sponsorshipThis work was supported by KOSEF through the MICROS at KAIST, Koreaen
dc.languageENG-
dc.language.isoen_USen
dc.publisherIEEE-
dc.titleA high-speed pattern decoder in MPEG-4 padding block hardware accelerator-
dc.typeConference-
dc.identifier.scopusid2-s2.0-0034996251-
dc.type.rimsCONF-
dc.citation.volume2-
dc.citation.publicationnameIEEE International Symposium on Circuits and Systems (ISCAS 2001)-
dc.identifier.conferencecountryAustralia-
dc.identifier.conferencecountryAustralia-
dc.contributor.localauthorKim, Lee-Sup-
dc.contributor.nonIdAuthorMo, H.-C.-
dc.contributor.nonIdAuthorKim, J.-S.-

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0