Low-area multi-mode 5G NR LDPC decoding architecture with efficient memory access scheduling

Abstract

Due to the high throughput demand of the 5G standard, the LDPC code is used instead of the Turbo code in the channel coding of 5G. At the same time, the 5G standard has various and irregular lifting sizes, unlike the existing standard to support messages of various lengths. Therefore, we would like to propose an area-efficient LDPC decoder that satisfies the throughput requirements of the 5G standard and supports all lifting sizes. Instead of using the maximum parallelism as in the implementation of the existing 5G LDPC decoder, we tried to achieve a low area by using lower parallelism. Therefore, we propose a memory access scheduling method that solves the data access and alignment problem caused by the partially parallel structure, layer skip method and a decoder structure based on proposed method. Compared with the existing decoder structure, it achieves the highest throughput per area while satisfying the throughput requirements of the 5G standard.