Area-efficient plane-wise FFT architecture for 5G NR communication systems

Abstract

Fast Fourier transform (FFT) is widely used in the orthogonal frequency division multiplexing (OFDM) systems to overcome the issues related to the generation of orthogonal subcarriers. This paper proposes a plane-wise time-multiplexing processing as a simple FFT processing method for 5th generation (5G) new radio (NR) communication systems, and a hardware architecture for it. The proposed method simplifies the FFT processing required in the 5G NR communication systems by dividing the entire FFT into several planes and time-multiplexing them, which makes the very-large-scale integration (VLSI) design simple. In addition, in order to reduce the size of the memory that occupies most of the area of the FFT hardware, precision tapering is proposed based on the fundamental property of FFT hardware implementation. Simulation results show that the precision tapering reduces the sizes of the delay buffer and twiddle factor memory by 4.18% and 17.14%, respectively, for the proposed FFT hardware architecture, while maintaining the signal-to-quantization-noise-ratio (SQNR) obtained with the previous uniform precision structure.