(A) 120 GHz CMOS quadrature phase-locked loop for wireless chip-to-chip communication

Abstract

This thesis proposes a 120 GHz quadrature phase-locked loop for CMOS-based short-range wireless chip-to-chip communication applications. First, the design requirements of the quadrature phase-locked loop for the 120 GHz, 16-QAM modulation system are analyzed: it is essential to have a phase noise of -90 dBc/Hz or less, a phase jitter of 93.3 fsec or less, and an image rejection ratio of 30 dBc or more at 120 GHz phase-locked loop, in conclusion. An integer-N phase-locked loop using an injection-locked frequency tripler is adopted to present an idea to satisfy the requirements. To ensure low phase noise and low phase jitter, proposed 120 GHz phase-locked loop consisting of a phase-locked loop operating in the 40 GHz band, an injection-locked frequency tripler in the 120 GHz band, and a hybrid coupler and I/Q correction circuit in the 120 GHz band are cascaded. A gate-source and source-gate feedback type 40 GHz colpitts oscillator with a feedback circuit that can further reduce the phase noise of the conventional transconductance-boosted colpitts oscillator is proposed and analyzed. In order to generate a high output power with low DC power consumption in the 120 GHz band, a broadband, high power efficiency injection-locked frequency tripler chain is analyzed: the proposed structure can extract harmonic power efficiently under low supply voltage. For wideband operation, a switching transformer inductor is proposed to extend the frequency lock range. In order to generate a quadrature signal, a hybrid coupler in the 100-140 GHz band is designed, and an I/Q correction circuit is also designed to control a quadrature phase control range of 20 degree and a gain control range of 1.5 dB to maximize the image rejection ratio. The phase-locked loop was fabricated through the 40-nm CMOS process, and the phase jitter of 353 fsec and the reference spur of -40 dBc or less are verified through the 40 GHz phase synchronization loop. The integrated 120 GHz phase-locked loop achieves 117.96 GHz, 363 fsec jitter, and an reference spur of -40 dBc or less. In addition, as a joint research, a hybrid coupler and an I/Q mismatch controller with the proposed injection-locked frequency tripler, is integrated in the D-band transmitter and receiver chipset, to verify the system requirements suggested at the beginning. This is verified by conducting an communication experiment. Finally, a data rate of 20 Gbps is obtained in the 120 GHz band with 16-QAM modulation.