DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Park, Chul Soon | - |
dc.contributor.advisor | 박철순 | - |
dc.contributor.author | Kang, Dong Min | - |
dc.date.accessioned | 2022-04-21T19:33:54Z | - |
dc.date.available | 2022-04-21T19:33:54Z | - |
dc.date.issued | 2021 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=956628&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/295644 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2021.2,[iv, 82 p. :] | - |
dc.description.abstract | This thesis proposes a 120 GHz quadrature phase-locked loop for CMOS-based short-range wireless chip-to-chip communication applications. First, the design requirements of the quadrature phase-locked loop for the 120 GHz, 16-QAM modulation system are analyzed: it is essential to have a phase noise of -90 dBc/Hz or less, a phase jitter of 93.3 fsec or less, and an image rejection ratio of 30 dBc or more at 120 GHz phase-locked loop, in conclusion. An integer-N phase-locked loop using an injection-locked frequency tripler is adopted to present an idea to satisfy the requirements. To ensure low phase noise and low phase jitter, proposed 120 GHz phase-locked loop consisting of a phase-locked loop operating in the 40 GHz band, an injection-locked frequency tripler in the 120 GHz band, and a hybrid coupler and I/Q correction circuit in the 120 GHz band are cascaded. A gate-source and source-gate feedback type 40 GHz colpitts oscillator with a feedback circuit that can further reduce the phase noise of the conventional transconductance-boosted colpitts oscillator is proposed and analyzed. In order to generate a high output power with low DC power consumption in the 120 GHz band, a broadband, high power efficiency injection-locked frequency tripler chain is analyzed: the proposed structure can extract harmonic power efficiently under low supply voltage. For wideband operation, a switching transformer inductor is proposed to extend the frequency lock range. In order to generate a quadrature signal, a hybrid coupler in the 100-140 GHz band is designed, and an I/Q correction circuit is also designed to control a quadrature phase control range of 20 degree and a gain control range of 1.5 dB to maximize the image rejection ratio. The phase-locked loop was fabricated through the 40-nm CMOS process, and the phase jitter of 353 fsec and the reference spur of -40 dBc or less are verified through the 40 GHz phase synchronization loop. The integrated 120 GHz phase-locked loop achieves 117.96 GHz, 363 fsec jitter, and an reference spur of -40 dBc or less. In addition, as a joint research, a hybrid coupler and an I/Q mismatch controller with the proposed injection-locked frequency tripler, is integrated in the D-band transmitter and receiver chipset, to verify the system requirements suggested at the beginning. This is verified by conducting an communication experiment. Finally, a data rate of 20 Gbps is obtained in the 120 GHz band with 16-QAM modulation. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Wireless Communication▼aquadrature▼aPLL▼aVCO▼ainjection-locked frequency multiplier | - |
dc.subject | 무선 통신▼a직교▼a위상 동기화 루프▼a전압제어발진기▼a주입동기식 주파수 체배기 | - |
dc.title | (A) 120 GHz CMOS quadrature phase-locked loop for wireless chip-to-chip communication | - |
dc.title.alternative | 무선 칩-투-칩 통신을 위한 120 GHz 직교 위상 동기 루프 연구 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | 강동민 | - |
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