Dynamic multi-bit successive cancellation list decoding of polar codes극 부호의 동적 다중비트 연속 제거 리스트 복호

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Polar codes are the first capacity-achieving error-correcting codes (ECC) which have attracted much research attentions. Among decoding methods, successive cancellation list decoding (SCLD) is considered as a representative decoding method to achieve good error-correction performance for finite length polar codes. However, the long latency of the SCLD is a significant problem to use it practically, which is mainly caused by two features of SCLD process : tree traversing and path splitting. To solve the main two reasons, a dynamic multi-bit successive cancellation list decoding (DM-SCLD) algorithm is proposed which decodes several bits simultaneously without traversing the tree to the leaf nodes. Furthermore, it reduces the path splitting, which is originally required when decoding every single bit, by finding a specific condition based on LLR values of the decoding tree nodes. In addition, an ignoring path(IP) technique is proposed to mitigate the condition of DM-SCLD which results in additional latency reduction compared to DM-SCLD. The simulation result show that the DM-SCLD with IP reduces clock cycles by 77%, 79% compared to conventional SCLD for List size = 8 and 16, respectively, with negligible error-correction performance degradation (<0.05dB).
Advisors
Park, In-Cheolresearcher박인철researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2020
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2020.8,[iii, 34 p. :]

Keywords

Polar codes▼asuccessive cancellation list decoding▼atree pruning▼athreshold▼aignoring path▼alow latency▼ahigh throughput▼aVLSI decoder architecture; 극부호▼a연속 제거 리스트 복호▼a트리제거▼a문턱▼a후보 무시▼a낮은 지연시간▼a높은 처리량▼aVLSI 복호기 구조

URI
http://hdl.handle.net/10203/285062
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=925226&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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