Analysis and optimization of metadata cache for secure memory overhead mitigation

Abstract

As part of secure processor design, secure memory techniques protect the confidentiality and integrity of external memory from physical attacks. Research over the past decades has matured this technique to some degree, leading the introduction of a commercial secure processor design adopting secure memory (Intel SGX). However, its performance overhead is still obstructing its wide adoption. The overhead basically comes from the extra memory accesses to metadata, which are necessary for the protection schemes of secure memory. To mitigate the overheads, various architectural designs or operational optimization techniques have been proposed. Among them, metadata cache was introduced in the early stage of research, for reducing both latency and traffic for metadata accesses. However, despite its importance, there are few in-depth studies on the characteristic metadata access or optimized cache design. In this dissertation, we examine the operation of secure memory based on the implementation of SGX. Then we analyze the access patterns for metadata and describe their unique features, including spatial locality based burst and hierarchical dependency. Based on these features, we propose metadata cache designs which improve the space utilization through burst and hierarchy aware cacheline protection and bypassing. We show that our design reduces average metadata cache miss rate by 7.4% and improves average performance by 3.4% for memory intensive workloads of SPEC2006.