Investigation of electrothermal annealing to enhance the reliability and the performance of field-effect transistors

Abstract

Controlling gate oxide quality has been considered the most important challenges to improving device performance, reliability and yield in CMOS technology. To mitigate the abovementioned damages, thermal annealing with the aid of a forming gas such as hydrogen ($H_2$) or deuterium ($D_2$) diluted with nitrogen ($N_2$), which is called wafer-level (global) forming gas annealing (FGA), has been widely used. During annealing, the forming gas passivates the trap sites at the interface of the Si-$SiO_2$, reduces the trap density, and cures pre-existing damage. However, the conventional FGA, which uses a furnace is not compatible with the metal interconnection process due to melting. An unexpected junction modification can be another concern. Moreover, local annealing to cure the damage in a selected cell or device is not possible with thermal annealing. To address these problems, in this thesis, localized electrothermal annealing (ETA) is investigated to enhance the device reliability of the MOFETs. Proposed annealing configuration utilizes Joule heat driven by the various currents (gate current, channel current, and body current) in MOSFETs. The annealing behaviors are discussed based on the numerical simulations and electrical measurements. As a further work, the ETA is proposed as a novel process to improve the performance of MOSFETs. In the view of dopant controlling, to fabricate an extremely scaled MOSFET with high packing density, the diffusion length of the implanted dopants needs to be precisely controlled to reduce the junction depth, to form abrupt junctions, and to reduce short-channel effects. However, as the scaling of the MOSFET reaches the physical limits of atomic scale, even the few seconds of annealing time required by RTA is becoming impractical. A novel annealing method with much faster operation and much higher temperature is needed.