(A) PVT-tolerant computing in-memory architecture for binary LSTM with customized 4T embedded DRAM cell array

Abstract

Long Short-Term Memory (LSTM) is widely used for sequential data processing such as speech recognition and machine translation, and massive number of weights with low reusability makes LSTM suitable for computing in-memory (CIM) approach. However, previous CIM architectures for binary neural networks suffer from high PVT variation, making them impractical to be employed in real-world devices. We propose a PVT-tolerant CIM architecture for binary LSTM based on a customized 4T embedded DRAM cell array. We implement time-multiplexed XNOR within a cell and PVT-tolerant accumulation by exploiting charge sharing. In result, the proposed architecture achieves 1.29x energy efficiency improvements and 14x stable accumulation over previous CIM architectures.