Design of low-power caches for mobile system

Abstract

After Apple releases iPhone in 2007 and Google releases Android in 2008, mobile computing systems became very popular due to their convenience and functionality. Most people use mobile computing devices likes smartphone in these days. Our daily lives are inevitably connected with these mobile devices, e.g., for communication, work, shopping, information, and news.

Mobile devices use battery for their portability. Due to limited power of battery, many people suffer from power shortage of mobile devices in their life. To prolong battery life, reducing power consumption of mobile device should be considered.

In this dissertation, we propose two scheme to reduce power consumption of cache memory, which is one of the most power consuming component in CPU. We research low-power cache for two kinds of memory

SRAM and STT-RAM.

(1) A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption

(2) MH Cache: A Multi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems

In the first scheme, we try to reduce the leakage energy consumption of SRAM cache. To achieve this, we propose a new cache architecture that can logically increase cache associativity of way-powered-down LLCs. Our proposed scheme is designed to be dynamic in activating an appropriate number of cache ways in order to eliminate the need for static profiling to determine an energy-optimized cache configuration. The experimental results show that our proposed dynamic scheme reduces the energy consumption of LLCs by 34% and 40% on single- and dual-core systems, respectively, compared with the best performing conventional static cache configuration. The overall system energy consumption including CPU, L2 cache, and DRAM is reduced by 9.2% on quad-core systems.

In the second scheme, we try to reduce the dynamic energy consumption of STT-RAM cache. We analyzed the memory access patterns of processes and observed that how rendering methods affect process behaviors. We propose a cache management scheme that measures write-intensity of each process dynamically and exploits it to manage a power-efficient multi-retention STT-RAM-based cache. Our proposed scheme uses variable threshold for a process's write-intensity to determine cache line placement. We explain how to deal with the following issue to implement our proposed scheme. Our experimental results show that our techniques significantly reduce the LLC power consumption by 32% and 32.2% in single- and quad-core systems, respectively, compared to a full STT-RAM LLC.