(A) high-speed data-equalizer compensating large ISI for wireline receivers유선통신 수신기들에서 큰 심볼간 간섭을 보상하는 고속 데이터 이퀄라이저

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As input data rate increases in wireline receivers, data loss gradually increases due to the limited bandwidth of the channel. Thus, the amount of inter-symbol interference (ISI) to compensate in a receiver is increasing. It is hard to compensate the high channel loss at a high target frequency with continuous time linear equalizer (CTLE). The other type of an equalizer, decision feedback equalizer (DFE) is to be used due to the mentioned issue. Therefore, DFE is implemented and problems caused by DFE are solved. To compensate the channel loss correctly with DFE, there is a constraint that feedback loop delay need to be within 1 unit-interval (UI). Thus, it is important to design a DFE which operates in high speed. To compensate a large ISI, multi-tap finite impulse response (FIR) DFE has been used but it lowers the maximum DFE speed due to the increased parasitic capacitance. Therefore, a high speed DFE which compensates a high channel loss is needed. Instead of multi-tap FIR DFE, an infinite impulse response (IIR) DFE which compensates high channel loss not using multi-taps has been used. However, when implementing an IIR DFE in sub-rate architecture to lower a clock frequency, it is hard to satisfy the 1 UI feedback time constraint because the full-rate multiplexer required in sub-rate IIR DFE increases the feedback loop delay. Note that the multiplexer used in a quarter-rate architecture is slower than the multiplexer used in a half-rate architecture resulting in the increased difficulty to satisfy the 1 UI feedback time constraint. The first proposed DFE (2 tap FIR DFE) controls a feedback tap weight by changing the common mode of the feedback signal to solve the aforementioned problem of the multi-tap FIR DFE. By doing that, the conventional tap weighting transistors (TWTs) are able to be removed resulting in the reduction of the parasitic capacitance so that the feedback loop delay is improved. Moreover, as the first tap weighting magnitude of the proposed DFE changes depending on the input data pattern, the compensation of large ISI is achieved with only 2 feedback taps. The test core fabricated in a 65 nm CMOS process achieves 0.0158 mW/Gbps/dB FOM compensating 22 dB channel loss in 0.9 V supply voltage for a 12 Gb/s input data rate. The second proposed DFE (1 tap FIR DFE) send a feedback signal to the clock path resulting in the reduction of the feedback loop delay unlike conventional DFEs which send the feedback signal to the data path. Moreover, the implementation of 1 tap FIR DFE is able to compensate a large channel loss because the tap weight becomes bigger in the larger ISI case. The test core fabricated in a 65 nm CMOS process achieves 0.0198 mW/Gbps/dB FOM compensating 19 dB channel loss in 0.87 V supply voltage for a 12.5 Gb/s input data rate. The third proposed DFE (quarter-rate 1 FIR 1 IIR DFE) proposes a single UI hold latch (SHL) so that the structure of the 4:1 multiplexer is simplified resulting in the improvement of the IIR feedback loop delay. Furthermore, unlike previous quarter-rate IIR DFEs which reduce only some part of the second post cursor ISI, the proposed DFE is able to reduce all part of the second post cursor ISI because the CMOS 4:1 multiplexer has a clock-less operation. The test core fabricated in a 65 nm CMOS process achieves 0.0164 mW/Gbps/dB FOM compensating 26 dB channel loss in 1 V supply voltage for a 10.8 Gb/s input data rate.
Advisors
Kim, Lee-Supresearcher김이섭researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2019
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2019.8,[vi, 48 p. :]

Keywords

Continuous-time linear equalizer(CTLE)▼aDecision-feedback equalizer(DFE)▼aFinite impulse response(FIR) DFE▼aInfinite impulse response (IIR) DFE▼aFeedback time improvement▼ahigh channel loss compensation; 연속 시간 선형 이퀄라이저▼a유한 임펄스 응답 결정 궤환 이퀄라이저▼a무한 임펄스 응답 결정 궤환 이퀄라이저▼a궤환 시간 개선; 큰 채널 손실 보상

URI
http://hdl.handle.net/10203/283301
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=871476&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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