High-speed massive time-interleaved SAR ADC for high-speed communication systems

Abstract

This paper presents a 7b 32GS/s SAR ADC using a massive time-interleaving (TI) architecture. For low-skew multi-phase clocks, generation utilizing a delay-locked loop (DLL), a phase-detector with reduced offset and dead-zone is proposed to minimize skews between the clocks. Different path delays by the distributed sub-ADCs over a large area in a massive TI ADC are compensated by multiplexing master clocks from the DLL. Offsets and skews in sub channels are calibrated on-chip in background via an additional dedicated sub channel. A prototype chip was implemented in a 40nm CMOS process with an active area of $0.207mm^2$. The measured SFDR and the SNDR of the prototype ADC at a 32GS/s conversion-rate are 43.1 dB and 31.4 dB, respectively. The ADC, including input buffers, consumes 125mW under a single 0.9V supply.