(A) low power source-synchronous injection-locked receiver with data equalization in near-threshold supply voltage

Abstract

This paper presents NTV source-synchronous injection-locked receivers. The receivers adopt two methods for the energy efficiency improvement. First is source synchronous injection-locked receiver. The clock sent with the data make high jitter correlation with the data. In addition, injection-locked oscillator makes low power consumption with optimum jitter correlation between clock and data. The second method is using the nearthreshold voltage as supply. The power consumption is proportional to square of supply. Therefore, the receiver can be implemented with very low power consumption. Using the NTV supply, however, it has some problems. As supply decreases, the variation of the delay more increases as the same supply variation. As a result, the clock recovery is vulnerable to supply noise. Another problem is channel loss compensation. A conventional CTLE has a large loading problem due to the high de-multiplexing ratio in NTV. As a result, CTLE cannot compensate large channel loss. A decision feedback equalizer has no loading problem, but it is difficult to satisfy the 1UI timing constraint because of the large delay in NTV. The first receiver is a 0.65V power noise tolerant source-synchronous injection-locked receiver with 13.4dB channel loss compensation. The power noise sensitivity of low supply is relieved by current and PMOS body bias control techniques of an oscillator. For the data equalization, the receiver has been adopted to DFE. To meet the 1UI timing constraint for the decision feedback equalizer in low supply, SR latches are removed in the feedback path, and return to zero recovered data is used for equalization. Additionally, the gain control of feedback signal is implemented to use of body bias control. Therefore the summer merged double tail latch can be simplified to lower power consumption. The test core fabricated in 65nm CMOS process achieves 11.2Gb/s with 0.303pJ/bit FOM compensating 13.4dB channel loss at 5.6GHz. The second receiver is a 0.65V source-synchronous injection-locked receiver with 13.6dB of target frequency channel loss and in-band channel loss compensation. For the data equalization, the receiver has adopted to a passive equalizer which has good energy efficiency. However, the passive equalizer has 20dB/decade compensation characteristic because of one pole system. As a result, the passive equalizer cannot compensate the loss of real channel which has not 20dB/decade characteristic. To solve the problem, dual-band passive equalization method is proposed for compensating the in-band channel loss as well as the target frequency loss. Additionally, in the injection-locked clock recovery circuit, CML to CMOS converter and pulse generator are replaced to AC coupling circuit which consists only passive components such as resistors and capacitors. Therefore the receiver has small power consumption. The test core fabricated in 65nm CMOS process achieves 8.4Gb/s with 0.0133pJ/bit/dB FOM which is best FoM among the recent low supply receivers. The third receiver proposes pseudo infinite impulse response (IIR) DFE. The conventional IIR DFE has the advantage to compensate large channel loss using only one tap. However, the data multiplexer which sums the demultiplexed data makes huge delay. As a result, the data multiplexer is difficult to use the low supply, especially in high clock and data de-multiplexing ratio. In the proposed receiver, to reduce the multiplexer delay, the clockless envelope detector is utilized. Furthermore, sense amplifier offset robust duty cycle corrector (DCC) is proposed in clock recovery circuit. In convention DCC, the time amplifier is added for offset robustness. The fourth receiver is proposed with compensation of passive equalizer DC loss and cascading equalizer for large channel loss compensation. The TA is inserted between first and second stage of the double tail latch (DTL) for compensating the DC loss. As a result, the small swing data output of passive equalizer can be recovered. As cascading equalizer, the first equalizer is utilized to the passive equalizer with time amplifier. The CLTE and DFE cannot be implemented due to large parasitic loading and delay problems. As an alternative solution, the FFE is utilized. Unlike the conventional FFE, two merged TAs and a transmission gate delay cell is used for feed forward the previous data with low power consumption.