Semi-Supervised Multi-Label Learning for Classification of Wafer Bin Maps With Mixed-Type Defect Patterns

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dc.contributor.authorLee, Hyuckko
dc.contributor.authorKim, Heeyoungko
dc.date.accessioned2020-12-28T15:10:04Z-
dc.date.available2020-12-28T15:10:04Z-
dc.date.created2020-11-30-
dc.date.issued2020-11-
dc.identifier.citationIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.33, no.4, pp.653 - 662-
dc.identifier.issn0894-6507-
dc.identifier.urihttp://hdl.handle.net/10203/279193-
dc.description.abstractAfter wafer fabrication, individual chips on the wafer are checked for defects by using multiple electrical tests. The test results can be represented by binary values for all individual chips, which form a spatial map called a wafer bin map (WBM). Different defect patterns in WBMs are related to different causes of process faults. Thus, it is important to classify WBMs according to their defect patterns to identify the root causes of process faults and correct the problems. Recently, with the increase in wafer size, the semiconductor manufacturing process has become more complicated and the probability of having mixed-type defect patterns in WBMs has increased. Previous studies for the classification of mixed-type defect patterns have mainly used labeled WBM data, although a much larger quantity of unlabeled data are often available in practice. To utilize both labeled and unlabeled data to achieve better classification performance, this study proposes the use of a semi-supervised deep convolutional generative model. In particular, we formulate the problem of classifying mixed-type defect patterns as a problem of multi-label classification and adopt multiple latent class variables, each for a distinct single pattern. As an inherent advantage of a generative model, we can also use the proposed model to generate new WBM data.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleSemi-Supervised Multi-Label Learning for Classification of Wafer Bin Maps With Mixed-Type Defect Patterns-
dc.typeArticle-
dc.identifier.wosid000587683500022-
dc.identifier.scopusid2-s2.0-85096039462-
dc.type.rimsART-
dc.citation.volume33-
dc.citation.issue4-
dc.citation.beginningpage653-
dc.citation.endingpage662-
dc.citation.publicationnameIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING-
dc.identifier.doi10.1109/TSM.2020.3027431-
dc.contributor.localauthorKim, Heeyoung-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorData models-
dc.subject.keywordAuthorSystematics-
dc.subject.keywordAuthorFeature extraction-
dc.subject.keywordAuthorSemiconductor device modeling-
dc.subject.keywordAuthorTraining-
dc.subject.keywordAuthorCircuit faults-
dc.subject.keywordAuthorIntegrated circuit modeling-
dc.subject.keywordAuthorMixed-type defect patterns-
dc.subject.keywordAuthorpattern classification-
dc.subject.keywordAuthorsemiconductor manufacturing process-
dc.subject.keywordAuthorsemi-supervised deep generative model-
dc.subject.keywordAuthorwafer bin map-
dc.subject.keywordPlusRECOGNITION-
dc.subject.keywordPlusMODEL-
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