DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Sung-Yool | ko |
dc.contributor.author | Jang, Byung Chui | ko |
dc.date.accessioned | 2020-12-08T12:30:15Z | - |
dc.date.available | 2020-12-08T12:30:15Z | - |
dc.identifier.uri | http://hdl.handle.net/10203/278104 | - |
dc.description.abstract | Provided is a memory- and logic device-integrated soft electronic system, the memory- and logic device-integrated soft electronic system including: a substrate 100; a plurality of bar-shaped first electrodes 110 stacked on the substrate; a resistance-variable material layer 120 coated on the lower electrode; and a plurality of bar-shaped second electrodes 130 stacked on the resistance-variable material layer 120, wherein the first electrode and the second electrode cross each other. | - |
dc.title | Memory and logic device-integrated soft electronic system | - |
dc.title.alternative | 메모리 및 논리소자 통합형 소프트 전자 시스템 | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | Choi, Sung-Yool | - |
dc.contributor.nonIdAuthor | Jang, Byung Chui | - |
dc.contributor.assignee | KAIST | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 16472218 | - |
dc.identifier.patentRegistrationNumber | 10847577 | - |
dc.date.application | 2017-06-30 | - |
dc.date.registration | 2020-11-24 | - |
dc.publisher.country | US | - |
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