Bitwise Competition Logic for compact digital comparator

Abstract

In this paper, we present a Bitwise Competition Logic (BCL) for the high performance and area efficient digital comparator. It compares two integer numbers using the location of the first 1 from the MSB, without arithmetic computations. The detail circuits to implement BCL, pre-encoder and selection logics are explained. The implemented BCL comparator shows 16%, 38% and 30% improved result in propagation delay, transistor count, and physical area compared to the other types of comparators. Measurement waveforms of fabricated BCL comparator verify its feasibility and functionality.