Spacer Engineering of Double Gate MOSFET: Performance Study Based on Quantum Transport Simulations

Abstract

Spacer property can affect device performances such as on/off-state current or subthreshold swing [1]. As technology node shrinks, the impact of spacer variation, such as dielectric constant of spacer and gate underlap, on device performances is becoming larger. Various parameters regarding spacer can degrade or enhance the performances of devices [2]. Although many simulation works considering spacer dependencies have been done, a lot of studies used TCAD to simulate spacer effect. However, various quantum effects such as tunneling and confinement should be considered in order to simulate short channel transistors precisely. Therefore more accurate simulation is needed in order to consider sub-10nm device. In this study, spacer effects on the device performances were studied in sub-10nm regime. Hamiltonian was extracted using tight binding method and a reduced basis transformation was used to reduce Hamiltonian size for efficient calculation [3]. The current-voltage characteristics were calculated by self-consistently solving non-equilibrium Green’s function and Poisson’s equation. We have found device performance significantly changes with space material and gate underlap length. As can be seen in Fig 2, changing spacer material from air to HfO2 result in the increase of on-state current by 61%.