Controller, semiconductor memory system and operating method thereof제어기, 반도체 기억 장치 시스템과 이의 작동 방법

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An operation method of a controller includes: generating a predetermined number of sub-messages by dividing an original message; generating a first parity added message by adding a cyclic redundancy check (CRC) parity message of a predetermined length to each of the sub-messages; and generating an encoded message by performing a polar encoding operation to the first parity added message.
Assignee
KAIST, SK Hynix Inc.
Country
US (United States)
Application Date
2017-08-02
Application Number
15666705
Registration Date
2019-10-08
Registration Number
10439647
URI
http://hdl.handle.net/10203/275205
Appears in Collection
EE-Patent(특허)
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