Low-power L1 instruction cache architecture based on horizontal indexing in embedded system

Abstract

We address reducing energy consumption method in Embedded System. The cache takes a lot of percentage in microprocessor. By reducing unnecessary energy consumption in the cache memory, the whole embedded system can reduce a lot of energy consumption. The cache reads whole horizontal cache line in one row, but only one datum is used among them. To use all the data which are read from the cache memory, this thesis suggests new indexing scheme, which is named horizontal indexing. By changing new indexing method, the number of accessing the cache can be reduced somewhat. This can mitigate energy consumption in whole embedded system. Utilizing line buffer which is smaller than the cache is the main reason of reducing dynamic energy consumption. This horizontal indexing cache architecture reduces energy consumption about 50 percentage compared to the baseline of cache. Also, as performance overhead is about 1 percentage, it does not affect the performance that much.