(A) study of high pressure low temperature deuterium annealing process effects on semiconductor devices

Abstract

The semiconductor and semiconductor device industries have evolved due to the continued miniaturization of the process patterning. However, as the process difficulty increases, it causes many problems in the development of the next generation memory. Especially, in order to improve the degradation of the characteristics due to the miniaturization of the DRAM and the NAND flash memory, many research groups and industries have been continuously studying. In this study, the Deuterium ($D_2$) annealing process is applied to the poly-crystalline silicon (poly-Si) channel device for NAND flash memory and the single-crystalline silicon (SC-Si) channel of DRAM provided in SK HYNIX. And the behavior of traps at the silicon channel to oxide interface and in the insulating oxide were quantified using DC I-V and low frequency noise method. As a result, subthreshold swing and mobility improvement were confirmed in both the poly-Si and the SC-Si channel with $D_2$ annealing. This suggests the possibility of replacing the Forming gas annealing (FGA), which is widely applied in the post-metal annealing process in the semiconductor industry, to the $D_2$ annealing process.