Design, modeling and signal integrity analysis of 3D X-pointmemory for high performance considering crosstalk and IR drop누화와 전압 강하를 고려한 고성능 삼차원 크로스포인트 메모리 디자인, 모델링 및 신호 무결성 분석

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For the $4^{th}$ industrial revolution, high density and high bandwidth memory are required in various applications. As the semiconductor process technology is developed, in memory hierarchy, the memory performance gap between conventional DRAM and NAND flash memory is widening. The Storage Class Memory (SCM) with high performance and non-volatility are needed to fill the gap. 3D X-Point Memory which is one of the SCM uses Phase Change Memory (PCM) and Ovonic Threshold Switch (OTS) with 2-stacked cross point array structure. Since the narrow space and long interconnection lines with 20 nm process technology, the crosstalk and IR Drop can occur and it decreases the memory endurance and causes the memory operation error. In this paper, 3D X-Point Memory for high performance considering crosstalk and IR drop is designed, modeled and analyzed with Signal Integrity (SI). For the SI analysis, core architecture is designed, PCM and OTS is behaviorally modeled, interconnection RC model and peripheral circuit models are proposed. The designed 3D X-Point memory is simulated, analyzed and verified the high performance considering crosstalk and IR drop.
Advisors
Kim, Jounghoresearcher김정호researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2018
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2018.8,[iv, 40 p. :]

Keywords

3D X-Point memory▼aphase change memory▼aovonic threshold switch▼acrosstalk▼aIR Drop; 삼차원 크로스 포인트 메모리▼a상변화 메모리▼a오보닉 문턱 스위치▼a누화▼a전압 강하

URI
http://hdl.handle.net/10203/266734
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=828563&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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