As devices such as UHD TVs, VR / AR headsets using high-definition video become popular, high speed interfaces
for supporting such devices are rapidly developing. In particular, HDMI 2.1, which was released in November 2017, is the most challenging interface with the highest data rate among these high-speed interfaces. In this thesis, we
will study Active HDMI 2.1 connector design. In particular, we will design for the HDMI 2.1 passive connector,
proposed the scalable RLCG model of HDMI assembled cable for channel characterization, and design a continuous-time linear equalizer that is inserted in the proposed active connector. The designed active connector will be verified by eye-diagram simulation.