Consecutive identical digits tolerant burst-mode clock and data recovery

Abstract

In PON system, Burst-mode CDR plays a key role in clock and data recovery. In up-stream data transmission, burst-mode CDR has to phase lock to each data packet sent from different ONUs in a short time for data recovery. Also, One of key factor in burst-mode CDR is to be tolerant to long run of CIDs input. Conventional burst-mode CDR has limited tolerance to long run of CIDs input. The three reasons of CIDs input tolerance degradation are phase error accumulation due to jitter, frequency mismatch between two VCOs and input data jitter. In this paper, we propose new type of burst-mode CDR tolerant to long run of CIDs input. Proposed burst-mode CDR is based on injection locking type. The burst-mode CDR has a function to inject fake data pulses to ILO to remove jitter accumulation during long run of CIDs input. We implement a DLL and a CID detector additionally for generating fake data and checking whether input data transition occurs or not respectively. When long run of CIDs input come into the CDR, the CID detector distinguishes CIDs input. Then readymade pulses having same phase with input data is injected to the ILO for keeping aligning its recovered clock to data center. Injecting fake data pulse to the ILO makes jitter accumulation in recov-ered clock removed during CIDs input period. Also, it makes recovered clock position well within a pulse. Our burst-mode CDR is tolerant to frequency mismatch between two VCOs due to nature of ILO. The frequency and phase of ILO is locked to fake data pulse which have same frequency and phase as input data. So, frequency mismatch between two VCOs is resolved by injection locking. Finally the jitter which is not filtered by an ILO is reduced by pulses injection process so it is tolerant to input data jitter. Proposed 5Gb/s burst-mode CDR was implemented by 65nm CMOS process with 28.96mW power consumption.