(An) area-efficient reconfigurable CNN-LSTM architecture for automatic speech recognition system음성인식 시스템을 위한 면적 효율적인 재구성 가능한 CNN-LSTM 아키텍처

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dc.contributor.advisorKim, Lee-Sup-
dc.contributor.advisor김이섭-
dc.contributor.authorKim, Hyunho-
dc.date.accessioned2019-09-04T02:40:31Z-
dc.date.available2019-09-04T02:40:31Z-
dc.date.issued2018-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=734200&flag=dissertationen_US
dc.identifier.urihttp://hdl.handle.net/10203/266726-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2018.2,[iv, 39 p. :]-
dc.description.abstractRecently, deep neural networks replace all stages of state-of-the-art automatic speech recognition (ASR) algorithms. Also, current segregated modules for voice activity detection (VAD) and speech recognition (SR) are highly area-inefficient. Therefore, we propose the first end-to-end neural network reconfigurable real-time ASR hardware architecture using a CNN-LSTM dual core system. The aggregation of separated modules and adaptation of the Winograd algorithm to CNN core both drastically reduce the overall area overhead. We further improve the energy efficiency by frame packaging scheme and partial power/clock gating onto the core. The proposed architecture achieves 61.2% area reduction and 93.6% energy reduction of always-on process.-
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectCMOS digital integrated circuits▼aSpeech recognition▼adeep neural network (DNN)▼aconvolutional neural networkc (CNN)▼along short-term memory (LSTM)▼aWinograd matrix multiplication▼adual core memory allocation-
dc.subjectCMOS 디지털 집적회로▼a음성인식▼a심층 신경회로망▼a컨볼루셔널 신경회로망▼a롱 쇼트-텀 메모리▼a위노그라드 매트릭스 곱 연산▼a듀얼 코어 메모리 할당-
dc.title(An) area-efficient reconfigurable CNN-LSTM architecture for automatic speech recognition system-
dc.title.alternative음성인식 시스템을 위한 면적 효율적인 재구성 가능한 CNN-LSTM 아키텍처-
dc.typeThesis(Master)-
dc.identifier.CNRN325007-
dc.description.department한국과학기술원 :전기및전자공학부,-
dc.contributor.alternativeauthor김현호-
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