Non-linear through-silicon via (TSV) and embedded capacitor modeling for analysis of bias-dependent power distribution network (PDN) in high bandwidth memory (HBM) systems

Abstract

In 2.5D and 3D IC systems, the low hierarchical power distribution network (PDN) impedance is desired to achieve low noise coupling to the PDN. To analyze 2.5D and 3D IC system PDN impedance accurate models of through-silicon via (TSV) and embedded capacitors are required. In this thesis, an explicit semiconductor physics based through-silicon via (TSV) capacitance-voltage (CV) model is proposed for the first time. The effect of TSV CV hysteresis and temperature is included in the TSV CV model. Moreover, equivalent circuit models of the embedded capacitors are proposed. The proposed models are verified with measurement results. The proposed model is applied to HBM system PDN impedance analysis, and the effect of bias voltage, number of chip layers and temperature on the PDN impedance is discussed.