Dummy Gate-Assisted n-MOSFET Layout for a Radiation-Tolerant Integrated Circuit

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A dummy gate-assisted n-type metal oxide semiconductor field effect transistor (DGA n-MOSFET) layout was evaluated to demonstrate its effectiveness at mitigating radiation-induced leakage currents in a conventional n-MOSFET. In the proposed DGA n-MOSFET layout, radiation-induced leakage currents are settled by isolating both the source and drain from the sidewall oxides using a P+ layer and dummy gates. Moreover, the dummy gates and dummy Metal-1 layers are expected to suppress the charge trapping in the sidewall oxides. The inherent structure of the DGA n-MOSFET supplements the drawbacks of the enclosed layout transistor, which is also proposed in order to improve radiation tolerance characteristics. The V-g - I-d simulation results of the DGA n-MOSFET layout demonstrated the effectiveness of eliminating such radiation-induced leakage current paths. Furthermore, the radiation exposure experimental results obtained with the fabricated DGA n-MOSFET layout also exhibited good performance with regard to the total ionizing dose tolerance.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2013-08
Language
English
Article Type
Article
Keywords

TECHNOLOGIES; CAPACITORS; DEVICES; OXIDES; CO-60; CMOS

Citation

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, v.60, no.4, pp.3084 - 3091

ISSN
0018-9499
DOI
10.1109/TNS.2013.2268390
URI
http://hdl.handle.net/10203/254749
Appears in Collection
EE-Journal Papers(저널논문)
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