A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise

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In this brief, we propose a hybrid phase locked loop (PLL) which employs a coarse resolution gated ring oscillator time-to-digital converter in the digital integral (I) path and a switched RC circuit in the analog proportional (P) path, which provide lower in-band noise than a bang-bang phase detector-based hybrid PLL (BB-HPLL). We also present noise analysis of the proposed PLL which shows that in-band noise can he further reduced by increasing the integral path gain, which is contrary to conventional design of BB-HPLLs where I path gain is minimized A prototype chip fabricated in the 65-nm CMOS achieves 13-dB improvement of in-band phase noise compared to a conventional hybrid PLL and 2.08 ps(rms) jitter at 4.8 GHz, while consuming 2.22 mW from a 1.0-V supply.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2019-02
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.2, pp.232 - 236

ISSN
1549-7747
DOI
10.1109/TCSII.2018.2848218
URI
http://hdl.handle.net/10203/251485
Appears in Collection
EE-Journal Papers(저널논문)
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