DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Dongin | ko |
dc.contributor.author | Cho, Seonghwan | ko |
dc.date.accessioned | 2019-03-19T01:04:27Z | - |
dc.date.available | 2019-03-19T01:04:27Z | - |
dc.date.created | 2019-02-25 | - |
dc.date.issued | 2019-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.2, pp.232 - 236 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | http://hdl.handle.net/10203/251485 | - |
dc.description.abstract | In this brief, we propose a hybrid phase locked loop (PLL) which employs a coarse resolution gated ring oscillator time-to-digital converter in the digital integral (I) path and a switched RC circuit in the analog proportional (P) path, which provide lower in-band noise than a bang-bang phase detector-based hybrid PLL (BB-HPLL). We also present noise analysis of the proposed PLL which shows that in-band noise can he further reduced by increasing the integral path gain, which is contrary to conventional design of BB-HPLLs where I path gain is minimized A prototype chip fabricated in the 65-nm CMOS achieves 13-dB improvement of in-band phase noise compared to a conventional hybrid PLL and 2.08 ps(rms) jitter at 4.8 GHz, while consuming 2.22 mW from a 1.0-V supply. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise | - |
dc.type | Article | - |
dc.identifier.wosid | 000458017900016 | - |
dc.identifier.scopusid | 2-s2.0-85048685566 | - |
dc.type.rims | ART | - |
dc.citation.volume | 66 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 232 | - |
dc.citation.endingpage | 236 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.identifier.doi | 10.1109/TCSII.2018.2848218 | - |
dc.contributor.localauthor | Cho, Seonghwan | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | hybrid PLL (HPLL) | - |
dc.subject.keywordAuthor | gated-ring oscillator (GRO) | - |
dc.subject.keywordAuthor | time-to-digital converter (TDC) | - |
dc.subject.keywordAuthor | bang-bang phase detector (BBPD) | - |
dc.subject.keywordPlus | TO-DIGITAL CONVERTER | - |
dc.subject.keywordPlus | FREQUENCY-SYNTHESIZER | - |
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