(A) study on the performance of gate insulator for adopting low resistance electrode and application to high resolution, large-sized AMOLED panel

Abstract

In this work, we investigate the performance of the various gate insulators (GI) in Cu top-gate-bottom-contact (TGBC) structured oxide TFTs, in order to adopt top-gate self-aligned structured TFT for reducing RC delay. In top gate structures, subsequent processes have a great effect on the electrical properties of oxide TFTs, because deposition of GI and post annealing are proceeded after oxide semiconductor film patterned. In particular, high performance barrier film is necessary since hydrogen content in semiconductor must be controlled precisely, so that high k dielectric material, $Al_2O_3$, is applied as the $1^{st}$ GI forming good interface with oxide active layer. In addition, double-layered GI including dielectric films by plasma enhanced chemical vapor deposition (PECVD) as the $2^{nd}$ GI is suggested, and the electrical performance of the oxide TFTs depending on the structure and materials of GI was examined. Meanwhile, low-resistance metal, Cu, easily diffuses into dielectric or semiconductors, resulting in degradation of TFT properties. Therefore, we fabricate Cu-TGBC oxide TFTs with SiNx as the barrier for preventing Cu diffusion, and verify the performance of the TFTs.