Low-cost transient error protections for memory systems

Abstract

Modern computing systems have been dramatically improved because of the continuing scaling of CMOS process technology. However, the miniaturization of process technology and increasing integration in nanometer regimes have made memory systems more vulnerable to various errors such as transient errors. In particular, cache and main memories are vulnerable to these errors because they operate at low voltage levels and include a large number of transistors. Moreover, the popular use of multi-level caches and growing memory size in general-purpose systems, even in embedded/mobile systems, increase the probability of errors occurring. Without proper protection of the memories, faults occurring in them will develop into errors, which will result in incorrect execution or system crash. To protect memory data from the transient errors, current memory systems typically employ error correcting codes (ECC), which incurs not only 12.5% of area overhead, but also increases computation delay and system power consumption. To address the overheads of conventional ECC schemes, this dissertation proposes four different low-cost error protection schemes. The first proposal is to effectively improve reliability of the tag array in the cache memories. Because of the spatial locality of programs, there are many tag bits whose values are the same with those of other tag bits in adjacent cache sets. This scheme exploits the tag bits similarity to improve reliability of tag bits against transient errors. When data are fetched from the main memory, it is checked if adjacent cache lines have the same tag bits as those of the data fetched. Using this same tag bit information, an error can be effectively corrected

the faulty tag bits is simply replaced with intact tag bits. The second proposal is to reduce ECC area overhead for cache data. The conventional ECC schemes for caches are based on a fifixed mapping between cache data words and ECC check bits, and fifixed ECC word granularity. This leads to inefficient usage of the ECC check bits. To effectively utilize ECC check bits, the proposed scheme protects only dirty cache words using a flexible mapping between SEC-DED check bits and dirty words, and variable SEC-DED word granularities. Finally, the proposed methods can reduce area overhead for error protection while maintaining the same performance as the conventional SEC-DED schemes. The third proposal, called SEA cache, is to minimizes ECC overheads, which further enhances the second proposal. SEA cache avoids the requirement for dedicated storage for ECC check bits, which are stored in cache lines as data. To effectively utilize cache space and enhance ECC efficiency, the proposed scheme groups several cache sets and manages them according to program behavior. SEA cache eliminates the considerable space overheads of conventional ECC schemes without noticeable reliability and performance degradation. The last proposal of this dissertation, called NZP, is to provide cost-effective ECC protections for the main memory. By exploiting relevant zero-valued data in the memory, NZP excludes storing zero-valued data, and the space used to store the zero data is assigned to ECC storage of nonzero-valued data. Further, strong ECC techniques are applied to data blocks with prevalent zero data space. Consequently, NZP can protect memory data and enhance reliability without requiring extra ECC space.