Engineering of vertically integrated nanowire in MOSFET and its application to versatile memory cells

Abstract

The vertically integrated five silicon nanowire (SiNW)-based field effect transistor (FET) with gate-all-around (GAA) configuration for high performance logic circuit and versatile memory is for the first time demonstrated in this work. Suppressing severe short channel effects(SCEs) stemming from continuous miniaturization, the transistor still serves as the most fundamental and core player in almost all electronic devices so far, and thus it is becoming increasingly important to satisfy its high performance and high power efficiency. In this regard, suggested transistor, i.e., the vertically integrated five GAA SiNW-based FET shows a potential for optimum transistor, encompassing a high-performance, good scalability, and low power consumption. Furthermore, the vertically integrated multiple nanowire configuration itself is very attractive for versatile application beyond an end use for logic circuit or memory device in this work. The configuration was created by the one-route all-dry etching process (ORADEP) optimized in this study, which showed high reproducibility, stiction-free stabil-ity, simplicity, and low variability of the fabrication process compared to previous result. The fabricated FET exhibited a high performance suitable for power-efficient logic circuit. Also, high sensing current for stable memory window and robust reli-ability was achieved from the FET, showing high practicality and suitability aimed at 3-dimensional (3-D) multifunctional memory with non-volatility and high-speed. Thus, this work suggests a blueprint for ultimate scaling of the transistor toward the roadmap end in view of performance and scalability, and more practically would serve as a core player in an innovative information and communication technology (ICT) product that can lead a “smart life” to be prevalent at upcoming future. In the first part, history of transistor to overcome SCEs and to meet high-performance is introduced, which naturally leads to the research motivation, accompanying with the drawbacks of previous works. In the second part, entire fabrication process including the ORADEP is introduced. In the third part, the superiority of the fabricated FET is proved via various application such as logic transistor, versatile memory device, and the FET with junctionless mode (JL) beyond inversion mode (IM).