Endurance-enhancing lower state encoding scheme for MLC and TLC NAND flash memory storage

Abstract

Endurance is a very important issue in NAND flash memory technology. The maximum number of program and erase (P/E) cycles, which is the lifetime of the NAND flash memory cell, falls significantly from single-level cell (SLC) through multi-level cell (MLC) to triple-level cell (TLC). Wear leveling, the general solution used to rectify this issue, enables cells to wear down evenly, but does not actually mitigate the wearing of the cells. Accordingly, techniques are needed for mitigation of cell degradation. This paper proposes Endurance-enhancing Lower State Encoding (ELSE)} scheme as a possible solution. The key insight leveraged by this proposed technique is the data pattern-related characteristic of NAND flash cell wear-out, where the lower cells have state, the less wear-out. When the bit patterns are appropriately changed to make the cell state as low as possible, the wear-out of the flash cell can be substantially reduced. To verify the efficacy of the proposed technique, we modeled threshold voltage ( $V_{th}$ ) using data from previous studies with actual NAND flash devices and performed experiments to show the improvement of lifetime. The experiments were conducted in both software and hardware implementations to explore the potential of practical feasibility from all possible aspects. Both the implementations are found to have the same effect on lifetime improvements but have different overheads. The results indicate that our proposed technique shows a maximum lifetime improvement of 478\% with negligible or acceptable overheads.